Add_full練習

課堂練習10/20

module AOI_4_Unit(y_out,X_in1,X_in2,X_in3,X_in4);

input X_in1,X_in2,X_in3,X_in4;

output y_out;

wire y1,y2;

and #1 (y1,X_in1,X_in2);

and #1 (y2,X_in3,X_in4);

nor #1 (y_out,y1,y2);

endmodule

module system_clock(clk);

parameter PERIOD = 100;

output clk;

reg clk;

initial clk = 0;

always

begin

#(PERIOD/2) clk = ~clk;

#(PERIOD/2) clk = ~clk;

#(PERIOD/2) clk = ~clk;

#(PERIOD/2) clk = ~clk;

end

always @(posedge clk)

if($time > 1000) #(PERIOD-1) $stop;

endmodule

module test;

wire X_in1,X_in2,X_in3,X_in4;

wire y_out;
system_clock #150 clock1(X_in1);

sysyem_clock #100 clock2(X_in2);

system_clock #50 clock3(X_in3);

system_clock #30 clock4(X_in4);
AOI_4_Unit AAA(y_out,X_in1,X_in2,X_in3,X_in4);
endmodule

實作..

module top;
wire a,b;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule

module Add_half(sum,c_out, a, b);

input a,b;
output sum,c_out;
wire c_out_bar;

xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);

endmodule

module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end

always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;

endmodule

HOMEWORK

module Add_half(sum,c_out,a,b);
input a,b;
out sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

上課實作08/09/22